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This book covers the design of next generation microprocessors in deep submicron CMOS technologies. The chapters in Design of High Performance Microprocessor Circuits were written by some of the world's leading technologists, designers, and researchers.
All levels of system abstraction are covered, but the emphasis rests squarely on circuit design. Examples are drawn from processors designed at AMD, Digital/Compaq, IBM, Intel, MIPS, Mitsubishi, and Motorola. Each topic of this invaluable reference stands alone so the chapters can be read in any order. The following topics are covered in depth.
William J Bowhill
Architectural constraints of CMOS VLSI design. Technology scaling, low-power devices, SOI, and process variations. Contemporary design styles including a survey of logic families, robust dynamic circuits, asynchronous logic, self-timed pipelines, and fast arithmetic units.
New York State Department O…
Latches, clocks and clock distribution, phase-locked and delay-locked loops. Register file, cache memory, and embedded DRAM design.
High-speed signaling techniques and I/O design. ESD, electromigration, and hot-carrier reliability. CAD tools, including timing verification and the analysis of power distribution schemes. Test and testability Design of High-Performance Microprocessor Circuits assumes a basic knowledge of digital circuit design and device operation, and covers a broad range of circuit styles and VLSI design techniques. Packed with practical know-how, it is an indispensable reference for practicing circuit designers, architects, system designers, CAD tool developers, process technologists, and researchers. It is also an essential text for VLSI design courses.
Rating: (not yet rated) Subjects. More like this. Find more information about: ISBN: 3368 OCLC Number: 557447535 Description: 1 online resource (xx, 557 pages): illustrations Contents: Part I. Overview - Chapter 1 Impact of Physical Technology on Architecture / John H.
Edmondson - Part II. Technology Issues - Chapter 2 CMOS Scaling and Issues in Sub-0.25 mum Systems / Yuan Taur - Chapter 3 Techniques for Leakage Power Reduction / Vivek De, Yibin Ye, Ali Keshavarzi, Siva Narendra, James Kao, Dinesh Somasekhar, Raj Nair, Shekhar Borkar - Chapter 4 Low-Voltage Technologies / Tadahiro Kuroda, Takayasu Sakurai - Chapter 5 Soi Technology and Circuits / Ghavam G. Shahidi, Fari Assaderaghi, Dimitri Antoniadis - Chapter 6 Models of Process Variations in Device and Interconnect / Duane Boning, Sani Nassif - Part III.
Circuit Styles for Logic - Chapter 7 Basic Logic Families / Kerry Bernstein - Chapter 8 Issues in Dynamic Logic Design / Paul Gronowski - Chapter 9 Self-Timed Pipelines / Ted Williams - Chapter 10 High-Speed VLSI Airthmetic Units: Adders and Multipliers / Vojin G. Oklobdzija - Part IV. Clocking - Chapter 11 Clocked Storage Elements / Hamid Partovi - Chapter 12 Design of High-Speed CMOS PLLs and DLLs / John George Maneatis - Chapter 13 Clock Distribution / Daniel W.
Bailey - Part V. Memory System Design - Chapter 14 Register Files and Chahes / Ronald Preston - Chapter 15 Embedded Dram / Tadaaki Yamauchi, Michihiro Yamada - Part VI. Interconnect and I/O - Chapter 16 Analyzing on-Chip Interconnect Effects / Noel Menezes, Lawrence Pileggi - Chapter 17 Techniques for Driving Interconnect / Shannon V.
Morton - Chapter 18 I/O and ESD Circuit Design / Stephen C. Thierauf, Warren R. Anderson - Chapter 19 High-Speed Electrical Signaling / Stefanos Sidiropoulos, Chih-Kong Ken Yang, Mark Horowitz - Part VII. Reliability - Chapter 20 Electromigration Reliability / J. Joseph Clement - Chapter 21 Hot Carrier Reliability / Kaizad Mistry - Part VIII. Cad Tools and Test - Chapter 22 Overview of Computer-Aided Design Tools / Yao-Tsung Yen - Chapter 23 Timing Verification / Victor Peng - Chapter 24 Design and Analysis of Power Distribution Networks / David Blaauw, Rajendran Panda, Rajat Chaudhry - Chapter 25 Testing of High-Performance Processors / Dilip K.
Responsibility: Anantha Chandrakasan, William J. Bowhill, Frank Fox, editors. More information:. Abstract. This book covers the design of next generation microprocessors in deep submicron CMOS technologies. The chapters in Design of High Performance Microprocessor Circuits were written by some of the world's leading technologists, designers, and researchers.
All levels of system abstraction are covered, but the emphasis rests squarely on circuit design. Examples are drawn from processors designed at AMD, Digital/Compaq, IBM, Intel, MIPS, Mitsubishi, and Motorola. Each topic of this invaluable reference stands alone so the chapters can be read in any order. The following topics are covered in depth. Architectural constraints of CMOS VLSI design.
Technology scaling, low-power devices, SOI, and process variations. Contemporary design styles including a survey of logic families, robust dynamic circuits, asynchronous logic, self-timed pipelines, and fast arithmetic units. Latches, clocks and clock distribution, phase-locked and delay-locked loops. Register file, cache memory, and embedded DRAM design.
High-speed signaling techniques and I/O design. ESD, electromigration, and hot-carrier reliability. CAD tools, including timing verification and the analysis of power distribution schemes.
Test and testability Design of High-Performance Microprocessor Circuits assumes a basic knowledge of digital circuit design and device operation, and covers a broad range of circuit styles and VLSI design techniques. Packed with practical know-how, it is an indispensable reference for practicing circuit designers, architects, system designers, CAD tool developers, process technologists, and researchers. It is also an essential text for VLSI design courses.